Integrated circuits are very complex devices that include multiple layers. Each layer may include conductive material, isolating material and/or semi-conductive materials. These various materials are arranged in patterns, usually in accordance with the expected functionality of the integrated circuit. The patterns also reflect the manufacturing process of the integrated circuits. It is noted that integrated circuits are manufactured by complex multi-staged manufacturing processes.
Commonly an integrated circuit includes a substrate, multiple conductive layers (also known as metal layers) and multiple dielectric layers. Conductive layers usually include conductors made of conductive materials, whereas the conductors are separated by isolating materials such as various oxides. The dielectric layers are located between the conductive layers in an interlaced manner. Conductors of distinct conductive layers may be connected to each other and/or to the substrate by conductive materials (termed interconnects or vias) located within the dielectric layers. The substrate may include semi-conducting materials and at least a portion of the substrate is connected to a virtual ground.
Various inspection and failure analysis techniques evolved for inspecting integrated circuits both during the fabrication stages, between consecutive manufacturing stages, either in combination with the manufacturing process (also termed “in line” inspection techniques) or not (also termed “off line” inspection techniques). Various optical as well as charged particle beam inspection tools and review tools are known in the art, such as the Compluss™ and SEMVision™ of Applied Materials Inc. of Santa Clara, Calif.
Manufacturing failures may affect the electrical characteristics of the integrated circuits. Some of these failures result from unwanted disconnections between various elements of the integrated circuits. These failures are known as “open”. Other failures result from unwanted connections between various elements of the integrated circuits. These failures may include unwanted connections between isolated conductors, unwanted connections between a conductor and the ground via the substrate. These failures are also known as “shorts”.
A well-known inspection technique is the “voltage contrast technique”. This technique usually includes a charging stage and an imaging stage. During the charging stage an electron beam is directed onto a portion of a test structure (usually a large sized pad that can be relatively easily located), whereas isolated and non-grounded conductors are charged, thus forming charged patterns. During the imaging stage an electron beam is scanned across the test pattern whereas voltage potential level of a scanned point is reflected by an intensity level of secondary electrons emitted from said point. Accordingly, the imaging stage provides charging patterns that may be compared to previously scanned test structures and/or to expected/ previously stored and/or calculated results.
Voltage contrast techniques are described in various publications, including U.S. Pat. No. 6,445,199 of Satya et al., U.S. Pat. No. 6,448,099 of Iacoponi et al., and U.S. Pat. No. 5,959,459 of Satya et el., all three patents are incorporated herein by reference.
Some prior art methods are based upon a comparison between grounded conductors and isolated conductors that remain charged after the charging stage. Some prior art methods are limited to highly isolated test structures, while some may impose strict limitation upon the “imaging” particle beam, such as a short duration or the inducement of minimal voltage changes. A prior art method that imposes strict limitations upon the “imaging” particle beam is described at “A dynamic single E-beam short/open testing technique”, M. Brunner, B. Lischke, Scanning Electron Microscopy/1985/III, pages 991-999, SEM Inc. which is also incorporated herein by reference.
A method that was tested on printed circuit boards is described at “Bare-board e-beam testing: The charge storage problem”, M. Brunner, N. Kolbenschlag and B. Lischke, Microelectronic Engineering 8 (1988) 25-35, Elsavier Science Publishers B.V. (North-Holland), which is also incorporated herein by reference. According to this method a scanning beam scans a circuit while a large holding beam stabilizes the charge of the tested circuit.
Thus there is a clear need for a compact system and method for enhancing the sensitivity of voltage contrast analysis. There is a further need to provide a voltage contrast analysis technique that is applicable to conductors that are not grounded. There is a need to provide a voltage contrast analysis technique that is applicable to conductors that are not highly isolated from the ground, are not electronically connected to fixed voltage sources and/or are not exposed to holding beam.